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我們在設(shè)計ESD電容的時候，電容的容值是有限的，額定電壓也是有限地，該如何去選取呢？總結(jié)如下：
Applied Voltage Levels
For a specific ESD test Level, the lower the value of capacitance under test, the greater the voltage applied.
Higher values of capacitance can withstand high levels of ESD pulses。
The actual applied voltage is also limited by air discharge, which is a function of the case size.
Capacitor Capabilites
ESD電壓大小和電容容值
對于特定ESD測試，容值越小，加到電容上的電壓越高，參考ESR放電模型可以得出這樣的結(jié)論。
電容容值大，可以抵抗較高的電平。實際加在電容上的電壓受空氣放電的影響，和外殼容器大小是相關(guān)的。
Dielectric materials and Rated Voltage
C0G will wishstand higher levels of ESD for the same voltage rating and capacitance value
Higher voltage ratings are important if higher ESD levels were going to be involved
For the same chip size, as the voltage rating increases, the maximum capacitance ailable decreases
填充材料和額定電壓
這里有幾點要注意的，首先C0G這種材質(zhì)的電容最穩(wěn)定也是性能的對于過ESD實驗來說，其次電容的額定電壓越大過高等級的ESD實驗越有幫助。最后同樣尺寸的電容，額定電壓增加時，容值是受限的（電容發(fā)展越來越快的情況下，這種情況在改善。）
Chip Size
Chip size has little effect on basic ESD capability,providing the same capacitance value is ailable at the same voltage rating
For smaller chip sizes, the maximumu ailabe capacitance at the same voltage rating decreases
Reduction of chip size should be evaluated carefully for ESD critical appliactions.This is  especially true if it is necessary to trade off voltage rating or capacitance value
Use of 0603 chip sizes will most likely result in lower ESD levels.Air Breakdown is a factor to be considered
Chip sizes samller than 0603 should not be used in ESD critical Applications
電容封裝大小
   電容大小對ESD能力影響不大，如果是同樣的容值和同樣的額定電壓的情況下。
   越小的封裝，其可實現(xiàn)的容值是受限制的，在額定電壓情況相同的條件下。
   減小電容封裝在嚴(yán)酷的ESD要求下需要謹慎。
   0603的電阻普遍用在低ESD要求下，空氣擊穿是一個主要因素。小于0603不能使用。
Voltage Coefficient
C0G dielectric materials are close to ideal, and are not affected by voltage coefficients
X7R dielectric materials are Ferro electric, this effect increase the voltage applied
Higher voltage ratings are again desirable to reduce the impact of the voltage coefficient on the voltage applied
Smaller size chips may also influence the impact of the voltage coefficient
電壓增加對容值的影響，C0G來說幾乎不變，X7R會增大，額定電壓高會削弱這種影響。小封裝也會對此起作用。
下面為實驗和分析數(shù)據(jù)，摘自KEMET分析報告


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